LPC1833FET256,551

The LPC1833FET256,551 is a 32-bit Microcontroller based on ARM Cortex-M3 core with RISC architecture operates at a maximum frequency of 180MHz. The ARM Cortex-M3 is a next generation core that offers system enhancements such as low power consumption, enhanced debug features and a high level of support block integration. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching. The device incorporates 512kB internal flash, 136kB internal RAM, 16kB EEPROM, a quad SPI Flash Interface (SPIFI), a State-configurable Timer/PWM (SCTimer/PWM) subsystem, two high-speed USB controllers, Ethernet, an external memory controller and multiple digital and analog peripherals and 164 general-purpose I/O pins.

• ARM Cortex-M3 built-in memory protection unit (MPU) supporting eight regions
• Non-maskable Interrupt (NMI) input
• JTAG and serial wire debug, serial trace, eight breakpoints and four watch points
• Enhanced trace module (ETM) and Enhanced trace buffer (ETB) support
• System tick timer
• Multiple SRAM blocks with separate bus access
• Crystal oscillator with an operating range of 1MHz to 25MHz
• 12MHz Internal RC oscillator trimmed to 3 % accuracy
• Ultra-low power RTC crystal oscillator
• External memory controller (EMC)
• SD/MMC card interface
• 8-channel General-purpose DMA controller
• Motor control PWM for three-phase motor control
• Quadrature encoder interface (QEI)
• Repetitive interrupt timer (RI Timer)
• Windowed watchdog timer
• Ultra-low power real-time clock (RTC)
• Alarm timer - can be battery powered
• Unique ID for each device
• Four reduced power modes - Sleep, deep-sleep, power-down and deep power-down
• Processor wake-up from sleep mode via wake-up interrupts from various peripherals
• Wake-up from deep-sleep, power-down and deep power down modes
• Brownout detect with four separate thresholds for interrupt and forced reset
• Power-on reset (POR)