74HC40103D,652

The 74HC40103D is a 8-bit synchronous Down Counter has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. In normal operation, the counter is decremented by one count on each positive-going transition of the clock. Counting is inhibited when the terminal enable input (TE\) is high. The terminal count output (TC\) goes low when the count reaches zero if TE\ is low and remains low for one full clock period. When the synchronous preset enable input (PE\) is low, data at the jam input (P0 to P7) is clocked into the counter on the next positive-going clock transition regardless of the state of TE\. When the asynchronous preset enable input (PL\) is low, data at the jam input (P0 to P7) is asynchronously forced into the counter regardless of the state of PE\, TE\ or CP. The jam inputs (P0 to P7) represent a single 8-bit binary word.

• Cascadable
• Synchronous or asynchronous preset
• Low-power dissipation
• CMOS Input levels
• Complies with JEDEC standard No. 7A

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