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Quantità | |
---|---|
1+ | € 4,000 |
10+ | € 3,990 |
25+ | € 3,970 |
50+ | € 3,960 |
100+ | € 3,950 |
250+ | € 3,930 |
500+ | € 3,920 |
Informazioni sui prodotti
Panoramica del prodotto
CY7C1020DV33-10ZSXI is a CY7C1020DV33 high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking chip enable (CE) and write enable (WE) inputs low. If byte low enable (BLE) is low, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A14). If byte high enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A14). Reading from the device is accomplished by taking chip enable active-low (CE) and output enable (OE) low while forcing the write enable (WE) high. If byte low enable (BLE) is low, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If byte high enable (BHE) is low, then data from memory will appear on I/O8 to I/O15.
- Pin-and function-compatible with CY7C1020CV33
- High speed is tAA = 10ns
- Low active power, ICC = 60mA at 10ns
- Low CMOS standby power, ISB2 = 3mA
- 2.0V data retention
- Automatic power-down when deselected
- CMOS for optimum speed/power
- Independent control of upper and lower bits
- 44-pin TSOP Type II package
- Industrial temperature range from –40°C to +85°C
Specifiche tecniche
512Kbit
512Kbit
da 3V a 3,6V
TSOP
44Pin
3V
3.3V
montaggio superficiale
85°C
-
SRAM asincrona
32K x 16 bit
32K x 16 bit
TSOP
10ns
3.6V
-
-40°C
-
No SVHC (21-Jan-2025)
Documenti tecnici (2)
Legislazione e ambiente
Certificato di conformità del prodotto